Taipei, July 19 (CNA) Taiwan Semiconductor Manufacturing Co. (TSMC), the world's largest contract chipmaker, said on Thursday that its 2-nanometer N2 chip is on track to begin mass production in 2025.
At an investor conference, TSMC Chairman C.C. Wei (魏哲家) said the development of the 2nm technology is progressing well, with its performance and yield meeting or exceeding expectations, therefore mass production is set to take place as planned.
The 2nm process will be 10-15 percent faster compared to the current N3E and consume less power, Wei said. Chip densities will also be higher by more than 15 percent.
He added that TSMC is also on track to launch the N2P and A16 processes in the second half of 2026.
The N2P is set to be an advanced version of the N2. It will boost performance by 5 percent and use 5-10 percent less power, making it suitable for smartphone and high-performance computing applications, Wei explained.
According to TSMC, the A16 is the next nanosheet-based technology to feature Super Power Rail or SPR.
SPR is a TSMC technology that enhances power delivery and efficiency in advanced semiconductors. It ensures better power distribution, reduced power loss, and improved chip performance.
Compared to the N2P process, the A16 will be 8-10 percent faster and use 15-20 percent less power, Wei said, adding that chip densities will be 7-10 percent higher.
Regarding InFO (integrated fan-out) wafer-level packaging, Wei said at the event that the company was still working on developing this technology.
Based on information released on TSMC's website, InFO is an innovative wafer level system integration technology platform, featuring high density RDL (Re-Distribution Layer) and TIV (Through InFO Via) for high-density interconnect and performance for various applications, such as mobile and high performance computing.
